integrated device technology, inc. description: the idt54/74fct377t/at/ct/dt are octal d flip-flops built using an advanced dual metal cmos technology. the idt54/ 74fct377t/at/ct/dt have eight edge-triggered, d-type flip- flops with individual d inputs and o outputs. the common buffered clock (cp) input loads all flip-flops simultaneously when the clock enable ( ce ) is low. the register is fully edge-triggered. the state of each d input, one set-up time before the low-to-high clock transition, is transferred to the corresponding flip-flops o output. the ce input must be stable only one set-up time prior to the low-to-high transi- tion for predictable operation. idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable military and commercial temperature ranges april 1995 1995 integrated device technology, inc. 6.14 dsc-4200/3 1 the idt logo is a registered trademark of integrated device technology, inc. features: ? std., a, c and d speed grades ? low input and output leakage 1 m a (max.) ? cmos power levels ? true ttl input and output compatibility C v oh = 3.3v (typ.) C v ol = 0.3v (typ.) ? high drive outputs (-15ma i oh , 48ma i ol ) ? power off disable outputs permit live insertion ? meets or exceeds jedec standard 18 specifications ? product available in radiation tolerant and radiation enhanced versions ? military product compliant to mil-std-883, class b and desc listed (dual marked) ? available in dip, soic, qsop, cerpack and lcc packages 2630 drw 01 ce cp d cp q d 0 o 0 d cp q d 1 o 1 d cp q d 2 o 2 d cp q d 3 o 3 d cp q d 4 o 4 d cp q d 5 o 5 d cp q d 6 o 6 d cp q d 7 o 7 functional block diagram
6.14 2 idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable military and commercial temperature ranges pin configurations dip/soic/qsop/cerpack top view lcc top view pin description pin names description d 0 ?d 7 data inputs ce clock enable (active low) o 0 C o 7 data outputs cp clock pulse input 2630 tbl 01 function table (1) inputs outputs operating mode cp ce ce do load 1 - lh h load 0 - ll l hold - h x no change h h x no change note: 2630 tbl 02 1. h = high voltage level h = high voltage level one setup time prior to the low-to-high clock transition l = low voltage level l = low voltage level one setup time prior to the low-to-high clock transition x = don't care - = low-to-high clock transition absolute maximum ratings (1) capacitance (t a = +25 c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf note: 1. this parameter is measured at characterization but not tested. symbol rating commercial military unit v term (2) terminal voltage with respect to gnd C0.5 to +7.0 C0.5 to +7.0 v v term (3) terminal voltage with respect to gnd C0.5 to v cc +0.5 C0.5 to v cc +0.5 v t a operating temperature 0 to +70 C55 to +125 c t bias temperature under bias C55 to +125 C65 to +135 c t stg storage temperature C55 to +125 C65 to +150 c p t power dissipation 0.5 0.5 w i out dc output current C60 to +120 C60 to +120 ma 2630 lnk 03 2630 lnk 04 notes: 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed v cc by +0.5v unless otherwise noted. 2. input and v cc terminals only. 3. outputs and i/o terminals only. 2630 drw 02 5 6 7 8 9 10 d 0 d 1 o 1 1 2 3 4 20 19 18 17 16 15 14 13 vcc 12 11 ce d 7 o 2 d 2 d 3 o 3 cp d 6 o 6 o 5 d 5 d 4 gnd o 4 o 0 o 7 p20-1 d20-1 so20-2 so20-8 & e20-1 index 15 14 18 17 16 5 6 7 8 4 l20-2 d 0 d 1 o 1 vcc ce d 7 o 2 d 2 d 3 o 3 cp d 6 o 6 o 5 d 5 d 4 gnd o 4 o 0 o 7 9 10 11 12 13 32 1 20 19 2630 drw 03
idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable military and commercial temperature ranges 6.14 3 dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = 0 c to +70 c, v cc = 5.0v 5%; military: t a = C55 c to +125 c, v cc = 5.0v 10% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2.0 v v il input low level guaranteed logic low level 0.8 v i ih input high current (4) v cc = max. v i = 2.7v 1 m a i il input low current (4) v cc = max. v i = 0.5v 1 m a i i input high current (4) v cc = max., v i = v cc (max.) 1 m a v ik clamp diode voltage v cc = min., i n = C18ma C0.7 C1.2 v i os short circuit current v cc = max. (3) , v o = gnd C60 C120 C225 ma v oh output high voltage v cc = min. i oh = C6ma mil. 2.4 3.3 v v in = v ih or v il i oh = C8ma coml. i oh = C12ma mil. 2.0 3.0 v i oh = C15ma coml. v ol output low voltage v cc = min. i ol = 32ma mil. 0.3 0.5 v v in = v ih or v il i ol = 48ma coml. i off input/output power off v cc = 0v, v in or v o 4.5v 1 m a leakage (5) v h input hysteresis 200 mv i cc quiescent power v cc = max. 0.01 1 ma supply current v in = gnd or v cc notes: 2630 tbl 05 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. the test limit for this parameter is 5 m a at t a = -55 c. 5. this parameter is guaranted but not tested.
6.14 4 idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable military and commercial temperature ranges power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply v cc = max. 0.5 2.0 ma current ttl inputs high v in = 3.4v (3) i ccd dynamic power supply v cc = max., outputs open v in = v cc 0.15 0.25 ma/ current (4) ce = gnd v in = gnd mhz one input toggling 50% duty cycle i c total power supply v cc = max., outputs open v in = v cc 1.5 3.5 ma current (6) f cp = 10mhz v in = gnd ce = gnd v in = 3.4v 2.0 5.5 one bit toggling v in = gnd f i = 5mhz 50% duty cycle v cc = max., outputs open v in = v cc 3.8 7.3 (5) f cp = 10mhz, 50% duty cycle v in = gnd ce = gnd v in = 3.4v 6.0 16.3 (5) eight bits toggling v in = gnd f i = 2.5mhz 50% duty cycle notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp/ 2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz. 2639 tbl 05
idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable military and commercial temperature ranges 6.14 5 switching characteristics over operating range notes: 2630 tbl 07 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 2630 tbl 06 idt54/74fct377t fct54/74fct377at com'l. mil. com'l. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay cp to on c l = 50pf r l = 500 w 2.0 13.0 2.0 15.0 2.0 7.2 2.0 8.3 ns t su set-up time high or low dn to cp 2.5 3.0 2.0 2.0 ns t h hold time high or low dn to cp 2.0 2.5 1.5 1.5 ns t su set-up time high or low ce to cp 4.0 4.0 3.5 3.5 ns t h hold time high or low ce to cp 1.5 1.5 1.5 1.5 ns t w clock pulse width, high or low 7.0 7.0 6.0 7.0 ns idt54/74fct377ct fct54/74fct377dt com'l. mil. com'l. mil. symbol parameter condition (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay cp to on c l = 50pf r l = 500 w 2.0 5.2 2.0 5.5 2.0 4.4 ns t su set-up time high or low dn to cp 2.0 2.0 2.0 ns t h hold time high or low dn to cp 1.5 1.5 1.0 ns t su set-up time high or low ce to cp 3.5 3.5 3.0 ns t h hold time high or low ce to cp 1.5 1.5 0.0 ns t w clock pulse width, high or low 6.0 7.0 3.0 ns
6.14 6 idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable military and commercial temperature ranges test circuits and waveforms test circuits for all outputs enable and disable times propagation delay switch position pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns test switch disable low enable low closed all other tests open open drain definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. set-up, hold and release times pulse width 2630 drw 04 2630 drw 05 2630 drw 06 2630 drw 07 2630 drw 08 2630 lnk 08
idt54/74fct377t/at/ct/dt fast cmos octal d flip-flop with clock enable military and commercial temperature ranges 6.14 7 ordering information idt x package x process blank b commercial mil-std-883, class b p d so l e q plastic dip cerdip small outline ic leadless chip carrier cerpack quarter-size small outline package 377t 377at 377ct 377dt octal d flip-flop w/clock enable xxxx device type fct 54 74 C55 c to +125 c 0 c to +70 c xx temperature range blank high drive x family 2630 drw 09
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